Reduced Instruction Set Computer (RISC) processors are well known. RISC processors have instructions that facilitate the use of techniques such as pipelining, thereby improving processing performance.
Conventional RISC processors cannot operate on data stored in memory. Therefore, data to be operated upon by the processor must first be moved from memory into a register of the processor using a load instruction. Additionally, results calculated by the processor must be moved from a register back to memory using a store instruction. As a result, the load and store instructions of a conventional RISC processor can create significant overhead in certain types of programs, especially programs that perform looping routines. This overhead can also limit the speed at which a program operates. Furthermore, programs with looping routines need instructions to maintain and update a loop counter. This also results in additional overhead.
What is needed is a new RISC processor that overcomes the limitations noted above.